ICS8521I-03 查看數據表（PDF） - Integrated Circuit Systems

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ICS8521I-03

LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS8521I-03

LOW SKEW, 1-TO-9

DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

GENERAL DESCRIPTION

The ICS8521I-03 is a low skew, 1-to-9 Differen-

,&6

tial-to-LVHSTL Fanout Buffer and a member of

HiPerClockS™ the HiPerClockS™ family of High Performance

Clock Solutions from ICS. The ICS8521I-03 has

two selectable clock inputs. Redundant clock

pairs, CLK0, nCLK0 and CLK1, nCLK1 can accept most stan-

dard differential input levels. The clock enable is internally syn-

chronized to eliminate runt pulses on the outputs during asyn-

chronous assertion/deassertion of the clock enable pin.

Guaranteed output skew and part-to-part skew characteris-

tics make the ICS8521I-03 ideal for today’s most advanced

applications, such as IA64 and static RAMs.

FEATURES

• 9 LVHSTL outputs

• Redundant differential CLK0, nCLK0 and CLK1, nCLK1 inputs

• CLKx, nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum output frequency: 500MHz

• Output skew: 50ps (maximum)

• Part-to-part skew: 250ps (maximum)

• Propagation delay: 1.6ns (maximum)

• VOH = 1V (maximum)

• 3.3V core, 1.8V output operating supply voltages

• -40°C to 85°C ambient operating temperature

BLOCK DIAGRAM

CLK_EN

CLK0

nCLK0

0

CLK1

nCLK1

1

CLK_SEL

D

Q

LE

PIN ASSIGNMENT

32 31 30 29 28 27 26 25

Q0

VDD 1

nQ0

CLK0 2

24 VDDO

23 Q3

Q1

nCLK0 3

22 nQ3

nQ1

Q2

CLK_SEL 4

CLK1 5

ICS8521I-03

21 Q4

20 nQ4

nQ2

nCLK1 6

19 Q5

Q3

GND 7

nQ3

CLK_EN 8

18 nQ5

17 VDDO

Q4

9 10 1 1 12 13 14 1 5 16

nQ4

Q5

nQ5

Q6

32-Lead LQFP

nQ6

7mm x 7mm x 1.4mm Package Body

Q7

Y Package

nQ7

Top View

Q8

nQ8

8521AYI-03

www.icst.com/products/hiperclocks.html

1

REV. A APRIL 29, 2003

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