OX16PCI952 查看數據表（PDF） - Oxford Semiconductor

零件编号

产品描述 (功能)

生产厂家

OX16PCI952

Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface

Oxford Semiconductor 

OXFORD SEMICONDUCTOR LTD.

OX16PCI952

6.4.3 UART FIFO Levels ‘UFL’ (Offset 0x08)

The receiver and transmitter FIFO levels of both UARTs is mirrored (shadowed) in this local configuration register, as follows.

Bits

7:0

15:8

23:16

31:24

Description

UART0 Receiver FIFO Level (RFL[7:0])

UART1 Receiver FIFO Level (RFL[7:0])

UART0 Transmitter FIFO Level (TFL[7:0])

UART1 Transmitter FIFO Level (TFL[7:0])

Read/Write

EEPROM

PCI

-

R

-

R

-

R

-

R

Reset

0x00h

0x00h

0x00h

0x00h

6.4.4 UART Interrupt Source Register ‘UIS’ (Offset 0x0C)

The Interrupt Source Register of each UART and the general data status, is mirrored (shadowed) in this local configuration

register, as follows.

Bits

5:0

11:6

15:12

16

17

30:18

31

Description

Read/Write

EEPROM

PCI

UART0 Interrupt Source Register (ISR[5:0])

-

R

UART1 Interrupt Source Register (ISR[5:0])

-

R

Reserved

-

R

UART0 Good-Data Status

-

R

UART1 Good-Data Status

-

R

Reserved

-

R

Global Good-Data Status. This bit is the logical AND of bits 16 and 17,

-

R

i.e. it is set if Good-Data Status of all internal UARTs is set.

Reset

01h

01h

0h

1

1

00h

1

Good-Data status for a given internal UART is set when all of the following conditions are met:

• ISR reads a level0 (no-interrupt pending), a level 2a (receiver data available), a level 2b (receiver time-out) or a level 3

(transmitter THR empty) interrupt

• LSR[7] is clear so there is no parity error, framing error or break in the FIFO

• LSR[1] is clear so no over-run error has occurred

If the device driver software reads a given channel’s receiver FIFO levels (from the UFL register) followed by the UIS register,

and the Good-Data status for that channel is set, the driver can remove the number of bytes indicated by the FIFO level without

the need to read the line status register of that channel. This feature enhances the driver efficiency.

For a given channel, if the Good-Data status bit is not set, then the software driver should examine the corresponding ISR bits.

If the ISR indicates a level 4 or higher interrupt, the interrupt is due to a change in the state of modem lines or detection of flow

control characters, for that channel. The device driver-software should then take appropriate measures as would in any other

550/950 driver. When ISR indicates a level 1 (receiver status) interrupt then the driver can examine the Line Status Register

(LSR) of the relevant channel. Since reading the LSR clears LSR[7], the device driver-software should either flush or empty the

contents of the receiver FIFO, otherwise the Good-Data status will no longer be valid.

The UART FIFO Level (UFL), the UART Interrupt Source register (UIS) and the Global Interrupt Status register (GIS) are

allocated adjacent address offsets (08h to 10h) in the Base Address Register. The device driver-software can read all of the

above registers in a single burst read operation. The location offset of the registers are such that the FIFO levels are usually read

before the status registers so that the status of the N characters indicated in the receiver FIFO levels are valid.

DS-0028 Jul 05

External-Free Release

Page 22

Share Link: