NOIL2SM1300A(2014) 查看數據表（PDF） - ON Semiconductor
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NOIL2SM1300A Datasheet PDF : 44 Pages
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NOIL2SM1300A
Table 9. INTERNAL REGISTERS
Block Register Name Address [6..0]
AFE
afepwd2
12
Bias block bandgap
13
Image
imcmodes
14
Core
Fix7
15
Fix8
16
imcbias1
17
imcbias2
18
imcbias3
19
Imcbias4
20
Data Block Fix9
21
Fix10
22
dataconfig1
23
dataconfig2
24
Fix11
25
dacvrefadc
26
Fix12
27
Fix13
28
Fix14
29
datachannel0_1
30
Field
[3:0]
[0]
[1]
[2]
[5:3]
[0]
[1]
[2]
[3]
[4]
[5]
[7:0]
[7:0]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[7:0]
[7:0]
[1:0]
[2]
[3]
[4]
[5]
[7:6]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[0]
[1]
[2]
[3]
[5:4]
Reset Value
Description
0x00
Power down adc_channel_2x 11 to 8
‘0’
Power down bandgap and currents
‘1’
External resistor
‘0’
External voltage reference
‘000’
Bandgap trimming
0
Power down
‘1’
Enable vrefcol regulator
‘1’
Enable precharge regulator
0
Disable internal bias for vprech
‘1’
Disable column load
‘0’
clkmain invert
0x00
Reserved, fixed value
0x00
Reserved, fixed value
‘1000’
Bias colfpn DAC buffer
‘1000’
Bias precharge regulator
‘1000’
Bias pixel precharge level
‘1000’
Bias column ota
‘1000’
Bias column unip fast
‘1000’
Bias column unip slow
‘1000’
Bias column load
‘1000’
Bias column precharge
0x20
Reserved, fixed value
0xC0
Reserved, fixed value
0x00
Reserved, fixed value
1
‘1’: Enables user upload of dacvrefadc register value
‘0’: Keeps default value
0
Enable PRBS generation
0
Reserved, fixed value
0
Reserved, fixed value
0x03
Training pattern inserted to sync LVDS receivers
0x2A
Training pattern inserted to sync LVDS receivers
0
Reserved, fixed value
0x84
Input to DAC to set the offset at the input of the ADC
0x80
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
0
Bypass the data block
0
Enables the FPN correction
0
Overwrite incoming ADC data by the data in the testpat
register
0
Reserved, fixed value
0x00
Pattern inserted to generate a test image
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11
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