LH5496 查看數據表（PDF） - Sharp Electronics

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LH5496

CMOS 512 × 9 FIFO

Sharp Electronics 

CMOS 512 × 9 FIFO

LH5496/96H

OPERATIONAL MODES (cont’d)

Depth Expansion

Depth expansion is implemented by configuring the

required number of FIFOs in Expansion mode. In this

arrangement, the FIFOs are connected in a circular fash-

ion with the Expansion Out pin (XO) of each device tied

to the Expansion In pin (XI) of the next device. One FIFO

in this group must be designated as the first load device.

This is accomplished by tying the First Load pin (FL) of

this device to ground. All other devices must have their

FL pin tied to a high level. In this mode, W and R signals

are shared by all devices, while internal logic controls the

steering of data. Only one FIFO will be enabled for any

given read cycle, so the common Data Out pins of all

devices are wire-ORed together. Likewise, the common

Data In pins of all devices are tied together.

In Expansion mode, external logic is required to gen-

erate a composite Full or Empty flag. This is achieved by

ORing the FF pins of all devices and ORing the EF pins

of all devices respectively. The Half-Full flag and

Retransmit functions are not available in Depth Expan-

sion mode.

W

DATA IN

9

D0 - D8

FULL

RS

XO

9

9

9

LH5496/96H

FF

EF

RS

FL Vcc

XI

XO

9

9

FF LH5496/96H EF

RS

FL Vcc

9

FF

XI

XO

LH5496/96H

9

EF

RS

FL

XI

Figure 19. FIFO Depth Expansion (1536 × 9)

R

DATA OUT

Q0 - Q8

EMPTY

5496-19

13

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