MAX1002CAX 查看數據表（PDF） - Maxim Integrated

零件编号

产品描述 (功能)

生产厂家

MAX1002CAX

Low-Power, 60Msps, Dual, 6-Bit ADC

Maxim Integrated 

Low-Power, 60Msps, Dual, 6-Bit ADC

N

N+1

ANALOG

INPUT

N+2

tAP

TNK+

(INPUT CLOCK)

DCLK

50%

tDCLK

1.4V

tPD

tSKEW

DATA OUT

1.4V

DATA VALID N - 1

DATA VALID N

Figure 8. MAX1002 Timing Diagram

Output Data Format

The conversion results are output on a dual 6-bit-wide

data bus. Data is latched into the ADC output latch fol-

lowing a pipeline delay of one clock cycle (Figure 8).

Output data is clocked out of the respective ADC’s data-

output pins (D_0 through D_5) on the rising edge of the

clock output (DCLK), with a DCLK-to-data propagation

delay (tPD) of 7.1ns. The MAX1002 outputs are TTL com-

patible.

Transfer Function

Figure 9 shows the MAX1002’s nominal transfer function.

Output coding is offset binary with 1LSB = FSR / 63.

111111

111110

111101

100001

100000

011111

011110

000011

000010

000001

000000

-FSR

2

0

FSR

1LSB

2

INPUT VOLTAGE

(_IN+ to _IN-)

Figure 9. Ideal Transfer Function

_______________________________________________________________________________________ 9

Share Link: