HIP6500CB 查看數據表（PDF） - Intersil
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HIP6500CB Datasheet PDF : 15 Pages
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HIP6500
3V3SB (Pin 3)
This pin is the output of the internal 3.3VSB regulator
(VOUT1). This internal regulator operates continuously for as
long as the 5VSB bias voltage is applied to the HIP6500.
This pin is monitored for under-voltage events.
VCLK (Pin 6)
This pin is the output of the internal 2.5V clock chip regulator
(VOUT4). This internal regulator operates only in active
states (S0, S1/S2) and is shut off during any sleep state,
regardless of the configuration of the chip. This pin is
monitored for under-voltage events.
Description
Operation
The HIP6500 controls 5 output voltages (Refer to Figures 1,
2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5VSB, and 12V bias input from
an ATX power supply. The IC is composed of two linear
controllers supplying the PCI slots’ 3.3VAUX power (VOUT3)
and the 2.5V RDRAM or 3.3V SDRAM memory power
(VOUT2), two linear regulators providing an always-present
3.3VSB (VOUT1), and a dedicated 2.5V clock chip supply
(VOUT4), a dual switch controller supplying the 5VDUAL
voltage (VOUT5), as well as all the control and monitoring
functions necessary for complete ACPI implementation.
Initialization
The HIP6500 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage, initiating 3.3VSB
soft-start operation after exceeding POR threshold. At 3ms
(typically) after 3.3VSB finishes its ramp-up, the ENxVDL
status and the memory voltage (VMEM) setting are latched in
and the chip proceeds to ramp up the remainder of the
voltages, as required.
Operational Truth Tables
The EN3VDL and EN5VDL pins offer a choice of 4
configurations in terms of the overall system architecture
and supported features. Tables 1-3 describe the truth
combinations pertaining to each of the three outputs.
TABLE 1. 3.3VDUAL OUTPUT (VOUT3) TRUTH TABLE
EN3VDL S5 S3 3V3DL
COMMENTS
0
1
1
3.3V S0, S1 States (Active)
0
1
0
3.3V S3
0
0
1
Note Maintains Previous State
0
0
0
3.3V S4/S5
1
1
1
3.3V S0, S1 States (Active)
1
1
0
3.3V S3
1
0
1
Note Maintains Previous State
1
0
0
0V S4/S5
NOTE: Combination Not Allowed.
As seen in Table 1, EN3VDL simply controls whether the
3.3VDUAL plane remains powered up during S4/S5 sleep
state.
TABLE 2. 5VDUAL OUTPUT (VOUT5) TRUTH TABLE
EN5VDL S5 S3 5VDL
COMMENTS
0
1
1
5V S0, S1 States (Active)
0
1
0
0V S3
0
0
1
Note Maintains Previous State
0
0
0
0V S4/S5
1
1
1
5V S0, S1 States (Active)
1
1
0
5V S3
1
0
1
Note Maintains Previous State
1
0
0
5V S4/S5
NOTE: Combination Not Allowed.
Similarly, Table 2 details the fact that EN5VDL status
controls whether the 5VDUAL plane supports the S3-S5
sleep states.
TABLE 3. 2.5/3.3VMEM OUTPUT (VOUT2) TRUTH TABLE
RSEL S5 S3 2.5/3.3VMEM
COMMENTS
1kΩ
1
1
2.5V
S0, S1 States (Active)
1kΩ
1
0
1kΩ
0
1
2.5V
Note
S3
Maintains Previous State
1kΩ
0
0
0V
10kΩ 1
1
3.3V
10kΩ 1
0
3.3V
10kΩ 0
1
Note
10kΩ 0
0
0V
NOTE: Combination Not Allowed.
S5
S0, S1 States (Active)
S3
Maintains Previous State
S5
As seen in Table 3, 2.5/3.3VMEM output is maintained in S3
(suspend to RAM) sleep state only. The dual-voltage support
accommodates both SDRAM as well as RDRAM type
memories.
Not shown in any of the tables are the 3.3VSB and the
2.5VCLK outputs. The 3.3VSB output powers up as soon as
the 5VSB ATX output is available. The 2.5VCLK output
operation is restricted by the chip’s POR and is only
available in active state (S0, S1). For additional information,
see the soft-start sequence diagrams.
Additionally, the internal circuitry does not allow the
transition from an S3 (suspend to RAM) state to an S4/S5
(suspend to disk/soft off) state or vice versa. The only ‘legal’
transitions are from an active state (S0, S1) to a sleep state
(S3, S5) and vice versa.
4-7
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