IS42S16100-5TL 查看數據表（PDF） - Integrated Silicon Solution

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IS42S16100-5TL

512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Silicon Solution 

IS42S16100

TWO BANKS OPERATION COMMAND TRUTH TABLE(1,2)

Previous State Next State

Operation

CS RAS CAS WE A11 A10A9-A0 BANK 0BANK 1 BANK 0BANK 1

DESL

HXXXXXX

Any Any

Any Any

NOP

LHHHXXX

Any Any

Any Any

BST

LHH LXXX

R/W/A I/A

I

I/A

I/A R/W/A

I/A

I

A

I/A

I

I/A

I/A

A

I/A

I

READ/READA

L H L H H H CA(3)

H H CA(3)

H L CA(3)

H L CA(3)

L H CA(3)

L H CA(3)

L L CA(3)

L L CA(3)

I/A R/W/A

R/W A

I/A R/W/A

R/W A

R/W/A I/A

A R/W

R/W/A I/A

A R/W

I/A RP

A

RP

I/A

R

A

R

RP I/A

RP

A

R

I/A

R

A

WRIT/WRITA

L H L L H H CA(3)

H H CA(3)

H L CA(3)

H L CA(3)

L H CA(3)

L H CA(3)

L L CA(3)

L L CA(3)

I/A R/W/A

R/W A

I/A R/W/A

R/W A

R/W/A I/A

A R/W

R/W/A I/A

A R/W

I/A WP

A WP

I/A W

A

W

WP I/A

WP A

W

I/A

W

A

ACT

L L H H H RA RA

L RA RA

Any

I

I

Any

Any A

A Any

PRE/PALL

L LHLXHX

X H X

H L X

H L X

L L X

L L X

R/W/A/I I/A

I/A R/W/A/I

I/A R/W/A/I

R/W/A/I I/A

R/W/A/I I/A

I/A R/W/A/I

I

I

I

I

I/A

I

R/W/A/I I

I

I/A

I R/W/A/I

REF

L L LHXXX

I

I

I

I

MRS

L L L L OPCODE

I

I

I

I

Notes:

1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address

2. The device state symbols are interpreted as follows:

I Idle (inactive state)

A Row Active State

R Read

W Write

RP Read With Auto-Precharge

WP Write With Auto-Precharge

Any Any State

3. CA: A8,A9 = don’t care.

Integrated Silicon Solution, Inc. — www.issi.com

19

Rev.  D

01/28/08

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