ADNS-2030 查看數據表（PDF） - Avago Technologies

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ADNS-2030

Low Power Optical Mouse Sensor

Avago Technologies 

Notes on Power up and the Serial Port

The sequence in which VDD, PD, SCLK and SDIO are set

during powerup can affect the operation of the serial

port. The diagram below shows what can happen shortly

after powerup when the microprocessor tries to read data

from the serial port.

This diagram shows the VDD rising to valid levels, at some

point the microcontroller starts its program, sets the SCLK

and SDIO lines to be outputs, and sets them high. It then

waits to ensure that the ADNS-2030 has powered up and

is ready to communicate. The microprocessor then tries

to read from location 0x00, Product_ID, and is expecting

a value of 0x03. If it receives this value, it then knows that

the communication to the ADNS-2030 is operational.

The problem occurs if the ADNS‑2030 powers up before

the microprocessor sets the SCLK and SDIO lines to be

outputs and high. The ADNS-2030 sees the raising of the

SCLK as a valid rising edge, and clocks in the state of the

SDIO as the first bit of the address (sets either a read or a

write depending upon the state).

In the case of SDIO low, then a read operation has

started. When the microprocessor begins to actually

send the address, the ADNS-2030 already has the first bit

of an address. When the 7th bit is sent by the micro, the

ADNS‑2030 has a valid address, and drives the SDIO line

high within 120 ns (see detail “A” in Figure 26 and Figure

27). This results in a bus fight for SDIO. Since the address

is wrong, the data sent back will be incorrect.

In the case of SDIO high, a write operation is started. The

address and data are out of synchronization, and the

wrong data will be written to the wrong address.

VDD

PD

SCLK

SDIO

Address � 0x00

Problem Area

Figure 34. Power up serial port sequence.

Data � 0x03

20

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