Read Operation
A read operation, which means that data is going from the
ADNS‑2030 to the microcontroller, is always initiated by the
micro-controller and consists of two bytes. The first byte
contains the address, is written by the micro-controller, and
has a “0” as its MSB to indicate data direction. The second
byte contains the data and is driven by the ADNS-2030.
The transfer is synchronized by SCLK. SDIO is changed on
falling edges of SCLK and read on every rising edge of SCLK.
The micro-controller must go to a high Z state after the last
address data bit. The ADNS-2030 will go to the high Z state
after the last data bit. (see detail “B” in Figure 29). One other
thing to note during a read operation is that SCLK will need
to be delayed after the last address data bit to ensure that
the ADNS-2030 has at least 100 µs to prepare the requested
data. This is shown in the timing diagrams below.
SCLK
Cycle #
SCLK
SDIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDIO Driven by Microcontroller
Figure 26. Read operation.
Detail "A"
SDIO Driven by ADNS-2030
Detail "B"
Detail "A"
Microcontroller
to ADNS-2030
SDIO handoff
SCLK
SDIO
A1
t HOLD
100 � s, min
60 ns, min
0 ns, min
A0
120 ns, min
Figure 27. Microcontroller to ADNS-2030 SDIO handoff.
120 ns, max
Hi-Z
D7
120 ns, max
D6
0 ns, min
Detail "B"
ADNS-2030 to
Microcontroller
SDIO handoff
SCLK
SDIO
120 ns, min
D0
Released by 2030
10 ns, max
R/W bit of next address
Driven by micro
Figure 28. ADNS-2030 to microcontroller SDIO handoff.
NOTE: The 120 ns high state of SCLK is the minimum data
hold time of the ADNS-2030. Since the falling edge of
SCLK is actually the start of the next read or write com-
mand, the ADNS-2030 will hold the state of D0 on the
SDIO line until the falling edge of SCLK. In both write and
read operations, SCLK is driven by the microcontroller.
Serial port communications is not allowed while PD
(Power Down) is high. See “Error Detection and Recovery”
regarding re-synchronizing via PD.
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