MT90863 查看數據表（PDF） - Zarlink Semiconductor Inc
零件编号
产品描述 (功能)
生产厂家
MT90863 Datasheet PDF : 46 Pages
| |||
Features
• 2,048 512 and 512 x 512 switching among
backplane and local streams
• Rate conversion between 2.048, 4.096 and
8.192 Mb/s
• Optional sub-rate switch configuration for
2.048 Mb/s streams
• Per-channel variable or constant throughput
delay
• Compatible to HMVIP and H.100 specifications
• Automatic frame offset delay measurement
• Per-stream frame delay offset programming
• Per-channel message mode
• Per-channel direction control
• Per-channel high impedance output control
• Non-multiplexed microprocessor interface
• Connection memory block programming
• 3.3 V local I/O with 5 V tolerant inputs and
TTL-compatible outputs
• IEEE-1149.1 (JTAG) Test Port
MT90863
3 V Rate Conversion Digital Switch
Data Sheet
September 2011
Ordering Information
MT90863AG 144 Pin PBGA Trays
MT90863AL1 128 Pin MQFP* Tubes
MT90863AG2 144 Pin PBGA** Trays, Bake & Drypack
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40C to +85C
Applications
• Medium and large switching platforms
• CTI application
• Voice/data multiplexer
• Support ST-BUS, HMVIP and H.100 interfaces
STio0/
FEi0
STio15/
FEi15
STio16/
FEi16
STio23/
FEi23
STio24
STio31
C16i
F0i
C4i/C8i
ODE
VDD VSS
ODE
Backplane
Interface
S/P
&
P/S
Converter
Timing
Unit
Multiple Buffer
Data Memory
(2,048 channels)
Output
Mux
Internal
Registers
Local
Connection
Memory High/Low
(512 locations)
Multiple Buffer
Data Memory
(512 channels)
Backplane
Connection
Memory
(2,048 locations)
Multiple Buffer
Data Memory
(512 channels)
Local
Interface
P/S
Converter
Local
Interface
S/P
Converter
Microprocessor Interface
Test Port
F0o C4o
DS CS R/W A7-A0 DTA D15-D0
TMS TDi TDo TCK TRST
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2011, Zarlink Semiconductor Inc. All Rights Reserved.
STo0
STo11
STo12
STo13
STo15
STi0
STi11
STi12
STi13
STi15
RESET
IC1
IC2
Share Link: 