MT90863AG(2000) 查看數據表（PDF） - Zarlink Semiconductor Inc
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MT90863AG Datasheet PDF : 35 Pages
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MT90863 Advance Information
The falling edge of the frame measurement signal
(FEi) is evaluated against the falling edge of the
frame pulse (F0i). Table 8 and Figure 8 describe the
frame alignment register.
Memory Block Programming
The MT90863 has two connection memories: the
backplane connection memory and the local
connection memory. The local connection memory is
partitioned into high and low parts. The IMS register
provides users with the capability of initializing the
local connection memory low and the backplane
connection memory in two frames. Bit 11 to bit 13 of
every backplane connection memory location will be
programmed with the pattern stored in bit 7 to bit 9 of
the IMS register. Bit 12 to 15 of every local
connection memory low location will be programmed
with the pattern stored in bits 3 to 6 of the IMS
register.
The block programming mode is enabled by setting
the memory block program (MBP) bit of the control
register high. When the block programming enable
(BPE) bit of the IMS register is set to high, the block
programming data will be loaded into bits 11 to 13 of
every backplane connection memory and bits 12 to
15 of every local connection memory low. The other
connection memory bits are loaded with zeros. When
the memory block programming is complete, the
device resets the BPE bit to zero. See Figure 7 for
the connection memory contents when the device is
in block programming mode.
Delay Through the MT90863
The switching of information from the input serial
streams to the output serial streams results in a
throughput delay. The device can be programmed to
perform time-slot interchange functions with different
throughput delay capabilities on a per-channel basis.
For voice applications, select variable throughput
delay to ensure minimum delay between input and
output data. In wideband data applications, select
constant throughput delay to maintain the frame
integrity of the information through the switch.
The delay through the device varies according to the
type of throughput delay selected in the LV/C and
BV/C bits of the local and backplane connection
memory as described in Table 16 and Table 19.
Variable Delay Mode (LV/C or BV/C bit = 0)
The delay in this mode is dependent only on the
combination of source and destination channels and
is independent of input and output streams.
Constant Delay Mode (LV/C bit or BV/C= 1)
In this mode a multiple data memory buffer is used
to maintain frame integrity in all switching
configurations.
Microprocessor Interface
The MT90863 provides a parallel microprocessor
interface for non-multiplexed bus structures. This
interface is compatible with Motorola non-multiplexed
buses. The required microprocessor signals are the
16-bit data bus (D0-D15), 8-bit address bus (A0-A7)
and 4 control lines (CS, DS, R/W and DTA). See
Figure 16 for Motorola non-multiplexed bus timing.
The MT90863 microprocessor port provides access
to the internal registers, connection and data
memories. All locations provide read/write access
except for the Data Memory and the Data Read
Register which are read only.
Memory Mapping
The address bus on the microprocessor interface
selects the internal registers and memories of the
MT90863. If the A7 address input is low, then the
registers are addressed by A6 to A0 as shown in
Table 4.
If the A7 is high, the remaining address input lines
are used to select the serial input or output data
streams corresponding to the subsection of memory
positions. For data memory reads, the serial inputs
are selected. For connection memory writes, the
serial outputs are selected.
The control, device mode selection and internal
mode selection registers control all the major
functions of the device. The device mode selection
register and internal mode selection register should
be programmed immediately after system power-up
to establish the desired switching configuration as
explained in the Frame Alignment Timing and
Switching Configurations sections.
The control register is used to control the switching
operations in the MT90863. It selects the internal
memory locations that specify the input and output
channels selected for switching.
Control register data consists of: the memory block
programming bit (MBP): the memory select bits
(MS0-2); and, the stream address bits (STA0-4). The
memory block programming bit allows users to
program the entire connection memory block, (see
Memory Block Programming section). The memory
select bits control the selection of the connection
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