HD74LV595A 查看數據表（PDF） - Hitachi -> Renesas Electronics

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HD74LV595A

8-bit Shift Registers with 3-state Outputs

Hitachi -> Renesas Electronics 

HD74LV595A

• VCC = 3.3 ± 0.3 V

Ta = 25°C

Item

Symbol Min Typ

Maximum

fmax

clock

frequency

80 150

55 130

Propagation tPLH/tPHL —

delay time

—

8.8

11.3

— 7.7

— 10.2

tPHL

— 8.4

— 10.9

Enable time tZH

tZL

Disable time tHZ

tLZ

Setup time tSU

— 7.5

— 9.0

— 5.9

— 12.1

3.5 —

8.0 —

8.0 —

3.0 —

Hold time

th

Pulse width tw

1.5 —

0.0 —

0.0 —

5.0 —

5.0 —

5.0 —

Max

—

—

13.0

16.5

11.9

15.4

12.8

16.3

11.5

15.0

11.7

15.7

—

—

—

—

—

—

—

—

—

—

Ta = –40 to 85°C

Min

Max

70

—

50

—

1.0

15.0

1.0

18.5

1.0

13.5

1.0

17.0

1.0

13.7

1.0

17.2

1.0

13.5

1.0

17.0

1.0

13.5

1.0

16.2

3.5

—

8.5

—

9.0

—

3.0

—

1.5

—

0.0

—

0.0

—

5.0

—

5.0

—

5.0

—

Test

Unit Conditions

MHz CL = 15 pF

CL = 50 pF

ns CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

CL = 15 pF

CL = 50 pF

ns CL = 15 pF

CL = 50 pF

ns CL = 15 pF

CL = 50 pF

ns

ns

ns

FROM

(Input)

TO

(Output)

SRCLK

RCLK

SRCLK

G

QH'

QA – QH

QH'

QA – QH

SER before SRCLK ↑

SRCLK ↑ before RCLK ↑

SRCLR low before RCLK

↑

SRCLR high (inactive)

before SRCLK ↑

SER after SRCLK ↑

SRCLK ↑ after RCLK ↑

SRCLR low after RCLK ↑

RCLK high or low

SRCLK high or low

SRCLR low

10

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