MC74HC160AD 查看數據表（PDF） - Motorola => Freescale

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MC74HC160AD

Presettable Counters High−Performance Silicon−Gate CMOS

Motorola => Freescale 

MC54/74HC160A MC54/74HC162A

LOAD

INPUTS

TYPICAL APPLICATIONS

CASCADING

N–Bit Synchronous Counters

INPUTS

INPUTS

H = COUNT

L = DISABLE

H = COUNT

L = DISABLE

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

TO

MORE

SIGNIFICANT

STAGES

RESET

CLOCK

OUTPUTS

OUTPUTS

OUTPUTS

NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on

number of stages. This limitation is due to set up times between Enable (Port) and Clock.

LOAD

ENABLE P

ENABLE T

CLOCK

RESET

INPUTS

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

OUTPUTS

Nibble Ripple Counter

INPUTS

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

OUTPUTS

INPUTS

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

TO

MORE

SIGNIFICANT

STAGES

OUTPUTS

High–Speed CMOS Logic Data

11

DL129 — Rev 6

MOTOROLA

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