LTC2188UP 查看數據表（PDF） - Linear Technology

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LTC2188UP

16-Bit, 20Msps Low Power Dual ADC

Linear Technology 

LTC2188

Power Requirements The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 9)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

CMOS Output Modes: Full Data Rate and Double Data Rate

VDD

OVDD

IVDD

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

(Note 10)

(Note 10)

DC Input

Sine Wave Input

l

1.7

1.8

1.9

V

l

1.1

1.8

1.9

V

l

42

50

mA

43

mA

IOVDD

PDISS

Digital Supply Current

Power Dissipation

LVDS Output Mode

Sine Wave Input, OVDD = 1.2V

DC Input

l

Sine Wave Input, OVDD = 1.2V

1.6

mA

75.6

90

mW

79.3

mW

VDD

OVDD

IVDD

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

(Note 10)

(Note 10)

Sine Input, 1.75mA Mode

Sine Input, 3.5mA Mode

l

1.7

1.8

1.9

V

l

1.7

1.8

1.9

V

45

mA

l

47

54

mA

IOVDD

PDISS

Digital Supply Current

(0VDD = 1.8V)

Power Dissipation

Sine Input, 1.75mA Mode

Sine Input, 3.5mA Mode

l

Sine Input, 1.75mA Mode

Sine Input, 3.5mA Mode

l

38

mA

74

83

mA

149

mW

218

247

mW

All Output Modes

PSLEEP

PNAP

PDIFFCLK

Sleep Mode Power

Nap Mode Power

Power Increase with Differential Encode Mode Enabled

(No increase for Nap or Sleep Modes)

1

mW

10

mW

20

mW

Timing Characteristics The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fS

Sampling Frequency

tL

ENC Low Time (Note 8)

(Note 10)

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

l

1

l

20

l

2

20

MHz

25

500

ns

25

500

ns

tH

ENC High Time (Note 8)

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

l

20

25

500

ns

l

2

25

500

ns

tAP

Sample-and-Hold Acquisition Delay Time

0

ns

SYMBOL PARAMETER

CONDITIONS

Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)

tD

ENC to Data Delay

CL = 5pF (Note 8)

tC

ENC to CLKOUT Delay

CL = 5pF (Note 8)

tSKEW

DATA to CLKOUT Skew

Pipeline Latency

tD – tC (Note 8)

Full Data Rate Mode

Double Data Rate Mode

MIN

TYP

MAX

UNITS

l

1.1

1.7

3.1

ns

l

1

1.4

2.6

ns

l

0

0.3

0.6

ns

6

Cycles

6.5

Cycles

2188f

7

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