MC100EL38DWG(2008) 查看數據表（PDF） - ON Semiconductor

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MC100EL38DWG
(Rev.:2008)

5V ECL ÷2, ÷4/6 Clock Generation Chip

ON Semiconductor 

MC100EL38

VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE

20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10

VCC EN DIV_SEL CLK CLK VBB MR VCC Phase_Out Phase_Out

* All VCC pins are tied together on the die.

Warning: All VCC and VEE pins must be externally connected

to Power Supply to guarantee proper operation.

Figure 1. Pinout Assignment (Top View)

CLK

CLK

EN

R

MR

DIVSEL

P2

R

P4/6

R

Phase

Out

R Logic

Q0

Q0

Q1

Q1

Q2

Q2

Q3

Q3

PHASE_OUT

PHASE_OUT

Figure 2. Logic Diagram

Table 1. PIN DESCRIPTION

Pin

Function

CLK, CLK

ECL Diff Clock Inputs

Q0, Q1; Q0, Q1

Q2, Q3; Q2, Q3

EN

ECL Diff ÷2 Outputs

ECL Diff ÷4/6 Outputs

ECL Sync Enable Input

MR

ECL Master Reset Input

DIVSEL

ECL Frequency Select Input

Phase_Out, Phase_Out ECL Phase Sync Diff. Signal Output

VBB

Reference Voltage Output

VCC

Positive Supply

VEE

Negative Supply

Table 2. FUNCTION TABLE

CLK

EN

MR

Z

L

L

ZZ

H

L

X

X

H

Z = Low-to-High Transition

ZZ = High-to-Low Transition

X = Don’t Care

Function

Divide

Hold Q0−3

Reset Q0−3

DIVSEL

L

H

Q2, Q3 OUTPUTS

Divide by 4

Divide by 6

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