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6. Pinning information
6.1 Pinning
/9&*
%
$
9&&
*1'
<
DDE
Fig 4. Pin configuration SOT353-1 and SOT753
74LVC1G02
Single 2-input NOR gate
/9&*
%
9&&
$
QF
*1'
<
DDE
7UDQVSDUHQWWRSYLHZ
Fig 5. Pin configuration SOT886
/9&*
%
$
9&&
QF
*1'
<
DDI
7UDQVSDUHQWWRSYLHZ
Fig 6. Pin configuration SOT891, SOT1115 and
SOT1202
6.2 Pin description
Table 3.
Symbol
B
A
GND
Y
n.c.
VCC
Pin description
Pin
TSSOP5 and X2SON5
1
2
3
4
-
5
/9&*
%
*1'
9&&
$
<
DDD
7UDQVSDUHQWWRSYLHZ
Fig 7. Pin configuration SOT1226 (X2SON5)
XSON6
1
2
3
4
5
6
Description
data input
data input
ground (0 V)
data output
not connected
supply voltage
74LVC1G02
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 29 November 2016
© Nexperia B.V. 2017. All rights reserved
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