NXP Semiconductors
11. Waveforms
HEF4040B
12-stage binary ripple counter
VI
MR input
VSS
VI
CP input
VSS
tPHL
VOH
Q0 or Qn
output
VOL
VOH
Qn + 1 output
VOL
VM
tW
tPLH
VM
1/fmax
trec
tW
tPLH
VM
tPHL
VM
tTLH
tPHL
tTHL
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Fig 5.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Transition times: transition time (tt) = HIGH LOW (tTHL) or LOW HIGH (tTLH) transition times.
Measurement points are given in Table 8, test circuit in Figure 6 and test data in Table 9
Waveforms showing propagation delays for MR to Qn and CP to Q0, minimum MR and CP pulse widths
Table 8. Measurement points
Supply voltage
Input
VDD
5 V to 15 V
VI
VDD or VSS
VM
0.5VDD
Output
VM
0.5VDD
HEF4040B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 17 November 2011
© NXP B.V. 2011. All rights reserved.
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