74VHC74(2014) 查看數據表（PDF） - Fairchild Semiconductor

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74VHC74
(Rev.:2014)

Dual D-Type Flip-Flop with Preset and Clear

Fairchild Semiconductor 

Connection Diagram

Logic Symbol

IEEE/IEC

Pin Description

Pin Names

D1, D2

CK1, CK2

CLR1, CLR2

PR1, PR2

Q1, Q1, Q2, Q2

Description

Data Inputs

Clock Pulse Inputs

Direct Clear Inputs

Direct Preset Inputs

Output

Truth Table

Inputs

Outputs

CLR PR D CK Q

Q Function

L

HXX

L

H Clear

H LXX H

L Preset

L

L X X H(1) H(1)

H HL

L

H

H HH

H

L

H HX

Qn

Qn No Change

Note:

1. This configuration is nonstable; that is, it will not persist

when preset and clear inputs return to their inactive

(HIGH) state.

©1992 Fairchild Semiconductor Corporation

74VHC74 Rev. 1.3.1

2

www.fairchildsemi.com

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