74ALVC16834ADGG 查看數據表（PDF） - NXP Semiconductors.
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74ALVC16834ADGG Datasheet PDF : 15 Pages
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Nexperia
74ALVC16834A
18-bit registered driver with inverted register enable; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
A1, A2, A3, A4, A5, A6,
A7, A8, A9, A10, A11, A12,
A13, A14, A15, A16, A17, A18
Y1, Y2, Y3, Y4, Y5, Y6,
Y7, Y8, Y9, Y10, Y11, Y12,
Y13, Y14, Y15, Y16, Y17, Y18
n.c.
LE
OE
CP
GND
VCC
Pin
54, 52, 51, 49, 48, 47,
45, 44, 43, 42, 41, 40,
38, 37, 36, 34, 33, 31
3, 5, 6, 8, 9, 10,
12, 13, 14, 15, 16, 17,
19, 20, 21, 23, 24, 26
1, 2, 55
28
27
30
4, 11, 18, 25, 32, 39, 46, 53, 56
7, 22, 35, 50
Description
data inputs
data outputs
no connected
latch enable input (active LOW)
output enable input (active LOW)
clock pulse input (active rising edge)
ground (0 V)
supply voltage
6 Functional description
Table 3. Function table [1]
Input
Output
OE
LE
CP
An
Yn
H
X
X
X
Z
L
L
X
L
L
L
L
X
H
H
L
H
↑
L
L
L
H
↑
H
H
L
H
H
X
Y0 [2]
L
H
L
X
Y0 [3]
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition.
[2] Y0 = Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low.
[3] Y0 = Output level before the indicated steady-state input conditions were established.
74ALVC16834A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 21 November 2017
© Nexperia B.V. 2017. All rights reserved.
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