PDI1284P11 查看數據表（PDF） - NXP Semiconductors.
零件编号
产品描述 (功能)
生产厂家
PDI1284P11 Datasheet PDF : 16 Pages
| |||
Nexperia
PDI1284P11
3.3 V parallel interface transceiver/buffer
Table 2.
Symbol
HLHO
HLHI
PLHO
VCC(B)
OEA
DIR
Pin description …continued
Pin
Description
24
host logic high output (cable)
25
host logic high input (cable)
30
peripheral logic high output (cable)
31, 42
supply voltage B (cable side 3 V/5 V)
34
A side output enable input (active LOW)
48
direction selection input
[1] Pin with pull-up resistor to load cable.
6. Functional description
6.1 Function selection
Table 3. Function table[1]
DIR
OEA
HD
X
X
X
X
X
X
X
X
L
X
X
H
X
X
L
X
X
H
H
X
L
H
X
H
L
L
X
L
H
X
L
H
X
Input
C14 to C17
HLHI
A9 to A13
A9 to A13
PLHI
PLHI
A1 to A8
A1 to A8
B1 to B8
-
B1 to B8
Output
A14 to A17
HLHO
Y9 to Y13
Y9 to Y13
PLHO
PLHO
B1 to B8
B1 to B8
A1 to A8
A1 to A8
-
Output type
TP
TP
RP
TP
OC
TP
RP
TP
TP
Z[2]
RP[2]
[1] An = side driving internal IC;
Bn = side driving external cable (bidirectional);
Cn = side receiving control signals from external cable;
H = HIGH voltage level;
L = LOW voltage level;
OC = Open Collector;
X = don’t care (control signals in);
Yn = side driving external cable (unidirectional);
Z = high impedance (high-Z) or 3-state;
TP = totem pole output;
RP = resistive pull-up: 1.4 kΩ (nominal) on B/Y/C cable side and VCC. However, while a B/Y side output is LOW as driven by a LOW
signal on the A side, that particular B/Y side resistor is switched off to stop current drain from VCC through it.
[2] When DIR = L and OEA = H, the output signal is isolated from the input signal. Signals B1 to B8 maintain a resistive pull-up of 1.4 kΩ on
the input for this mode.
PDI1284P11_3
Product data sheet
Rev. 03 — 25 August 2008
© Nexperia B.V. 2017. All rights reserved
5 of 16
Share Link: 