74LVT640DB 查看數據表（PDF） - NXP Semiconductors.
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74LVT640DB Datasheet PDF : 15 Pages
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Nexperia
5 Pinning information
74LVT640
3.3 V Octal transceiver with direction pin; inverting; 3-state
5.1 Pinning
74LVT640
DIR 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
GND 10
20 VCC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
aaa-026618
Figure 3. Pin configuration for SO20
74LVT640
DIR 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
GND 10
20 VCC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
aaa-026619
Figure 4. Pin configuration for (T)SSOP20
5.2 Pin description
Table 2. Pin description
Symbol
DIR
A0, A1, A2, A3, A4, A5, A6, A7
GND
B0, B1, B2, B3, B4, B5, B6, B7
OE
VCC
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
18, 17, 16, 15, 14, 13, 12, 11
19
20
Description
direction control input
data inputs/outputs
ground (0 V)
data inputs/outputs
output enable input (active LOW)
supply voltage
6 Functional description
Table 3. Function selection [1]
Inputs
OE
DIR
L
L
L
H
H
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high impedance OFF-state.
Inputs/outputs
An
Bn
inputs
Z
Bn
inputs
An
Z
74LVT640
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 10 April 2017
© Nexperia B.V. 2017. All rights reserved.
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