8701CYILF 查看數據表（PDF） - Integrated Device Technology
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8701CYILF Datasheet PDF : 14 Pages
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ICS8701I
LOW SKEW, ÷1, ÷2
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
2, 5, 11,
26, 32, 35,
41, 44
VDDO
Power
Output supply pins.
7, 9, 18, 21,
28, 30, 37,
GND
Power
Power supply ground.
39, 46, 48
16, 20
25, 27, 29,
31, 33
VDD
Power
QA0, QA1, QA2,
QA3, QA4
Output
Positive supply pins.
Bank A outputs.LVCMOS / LVTTLinterface levels.
7Ω typical output impedance.
34, 36, 38,
40, 42
QB0, QB1, QB2,
QB3, QB4
Output
Bank B outputs.LVCMOS / LVTTLinterface levels.
7Ω typical output impedance.
43, 45, 47,
1, 3
QC0, QC1, QC2,
QC3, QC4
Output
Bank C outputs.LVCMOS / LVTTLinterface levels.
7Ω typical output impedance.
4, 6, 8,
10, 12
QD0, QD1, QD2,
QD3, QD4
Output
Bank D outputs. LVCMOS / LVTTLinterface levels.
7Ω typical output impedance.
22
CLK
Input Pulldown LVCMOS / LVTTL clock input.
13
DIV_SELD
Input
Pullup
Controls frequency division for Bank D outputs.
LVCMOS / LVTTLinterface levels.
14
DIV_SELC
Input
Pullup
Controls frequency division for Bank C outputs.
LVCMOS / LVTTLinterface levels.
23
DIV_SELB
Input
Pullup
Controls frequency division for Bank B outputs.
LVCMOS / LVTTLinterface levels.
24
DIV_SELA
Input
Pullup
Controls frequency division for Bank A outputs.
LVCMOS / LVTTLinterface levels.
17, 19
BANK_EN1,
BANK_EN0
Input
Pullup
Enables and disables outputs by banks.
LVCMOS / LVTTLinterface levels.
Master Reset and output enable. When HIGH, output drivers are
15
nMR/OE
Input Pullup enabled. Whe LOW, output drivers are in HiZ and dividers are reset.
LVCMOS / LVTTLinterface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8701CYI
www.idt.com
2
REV. C JULY 27, 2010
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