SSTDPAD2 查看數據表（PDF） - New Jersey Semiconductor
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SSTDPAD2 Datasheet PDF : 2 Pages
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Figure 1. Operational Amplifier Protection
Input Differential Voltage limited to 0.8V(typ) by DPADs DI and D2 Common
Mode Input voltage limited by DPADs Ds and 04 to ±15V.
Figure 2. Sample and Hold Circuit
Typical Sample and Hold circuit with clipping. DPAD diodes reduce offset
voltages fed capacitively from the JFET switch gate.
FIGURE 1
DPAD10
D1 Y.D2
Fo-
+15V -15V
FIGURE 2
+V -V
+v
o
DPAD1 T "
D1
i
ein CONTROL,
SIGNAL
2N4393
C i=
TO-72
Four Lead
TO-78
0.335
0034
SOIC
0.014
0.018
L5
0021 ~l
o.oso
0.189
0.196
Jl
0.150 t_
0.157
0.0075
0.0098
L.
r 0.0040
0.0098
KL-
0.2284
^^ 0.2440
DIMENSIONS IN
INCHES
All dimensions in inches
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