DM74ALS165(2007) 查看數據表（PDF） - Fairchild Semiconductor
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DM74ALS165 Datasheet PDF : 7 Pages
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Function Table
Inputs
Internal Outputs
Shift/Load Clock Inhibit
L
X
Clock
X
Serial Parallel A...H QA
X
a...h
a
QB
Output QH
b
h
H
L
L
X
X
QA0
QB0
QH0
H
L
↑
H
X
H
QAn
QGn
H
L
↑
L
X
L
QAn
QGn
H
↑
L
H
X
H
QAn
QGn
H
↑
L
L
X
L
QAn
QGn
H
H
X
X
X
QA0
QB0
QH0
H = HIGH Level (steady-state)
L = LOW Level (steady-state)
X = Don't Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
a...h = The level of steady-state input at inputs A through H, respectively
QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were
established
QAn, QGn = The level of QA or QG, respectively, before the most recent ↑ transition of the clock
Logic Diagram
©1986 Fairchild Semiconductor Corporation
DM74ALS165 Rev. 1.2
2
www.fairchildsemi.com
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