CY7C1061AV33-10ZXC(2007) 查看數據表（PDF） - Cypress Semiconductor

零件编号

产品描述 (功能)

生产厂家

CY7C1061AV33-10ZXC
(Rev.:2007)

16-Mbit (1M x 16) Static RAM

Cypress Semiconductor 

CY7C1061AV33

Switching Waveforms (continued)

Write Cycle No. 1 (CE1 or CE2 Controlled) [15, 16]

ADDRESS

CE1

tWC

tSCE

CE2

WE

tSA

tAW

tHA

tPWE

BHE/BLE

tBW

OE

DATA IO NOTE 17

tHZOE

Write Cycle No. 2 (WE Controlled, OE LOW) [15, 16]

tSD

tHD

VALID DATA

ADDRESS

CE1

tWC

tSCE

CE2

BHE/BLE

tSA

WE

tBW

tAW

tPWE

DATA IO

NOTE 17

tHZWE

tSD

VALID DATA

Notes

15. Data IO is high impedance if OE, or BHE or BLE or both = VIH.

16. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

17. During this period, the IOs are in output state and input signals should not be applied.

Document #: 38-05256 Rev. *G

tHA

tHD

tLZWE

Page 6 of 10

[+] Feedback

Share Link: