74AC573SC(1999) 查看數據表（PDF） - Fairchild Semiconductor

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74AC573SC
(Rev.:1999)

Octal Latch with 3-STATE Outputs

Fairchild Semiconductor 

Functional Description

The 74AC573 and 74ACT573 contain eight D-type latches

with 3-STATE output buffers. When the Latch Enable (LE)

input is HIGH, data on the Dn inputs enters the latches. In

this condition the latches are transparent, i.e., a latch out-

put will change state each time its D-type input changes.

When LE is LOW the latches store the information that was

present on the D-type inputs a setup time preceding the

HIGH-to-LOW transition of LE. The 3-STATE buffers are

controlled by the Output Enable (OE) input. When OE is

LOW, the buffers are enabled. When OE is HIGH the buff-

ers are in the high impedance mode but this does not inter-

fere with entering new data into the latches.

Truth Table

Inputs

OE

LE

D

L

H

H

L

H

L

L

L

X

H

X

X

H = HIGH Voltage

L = LOW Voltage

Z = High Impedance

X = Immaterial

O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable

Outputs

On

H

L

O0

Z

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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