ISP1583ET 查看數據表（PDF） - NXP Semiconductors.

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ISP1583ET

Hi-Speed USB peripheral controller

NXP Semiconductors. 

NXP Semiconductors

ISP1583

Hi-Speed USB peripheral controller

Table 16. Operation truth table for OTG

ISP1583 operation

VCC(3V3)

SRP is not applicable

SRP is possible

3.3 V

3.3 V

Power supply

VCC(I/O) RPU

(3.3 V)

3.3 V 3.3 V

3.3 V 3.3 V

VBUS

5V

0V

OTG register

not applicable

operational

8.16.3 Bus-powered mode

5 V-to-3.3 V

VOLTAGE

REGULATOR

VCC(3V3)

VBUS

VBUS

USB

1.65 V to 3.6 V

ISP1583

1.5 kΩ

VCC(I/O)

RPU

1 µF

1 MΩ

004aaa463

VCC(I/O) is powered by VBUS.

Fig 16. Bus-powered mode

In bus-powered mode (see Figure 16), VCC(3V3) and VCC(I/O) are supplied by the output of

the 5 V-to-3.3 V voltage regulator. The input to the regulator is from VBUS. On plugging the

USB cable, the ISP1583 goes through the power-on reset cycle. In this mode, OTG is

disabled.

Table 17. Operation truth table for SoftConnect

ISP1583 operation

Power supply

VCC(3V3) VCC(I/O) RPU

(3.3 V)

Normal bus operation

3.3 V 3.3 V 3.3 V

Power is lost

0V

0V

0V

VBUS

5V

0V

Bit SOFTCT in

Mode register

enabled

not applicable

Table 18. Operation truth table for clock off during suspend

ISP1583 operation

Power supply

VCC(3V3) VCC(I/O) RPU

(3.3 V)

Clock will wake up:

3.3 V 3.3 V 3.3 V

After a resume and

After a bus reset

Power is lost

0V

0V

0V

VBUS

5V

0V

Clock off

during suspend

enabled

not applicable

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

© NXP B.V. 2008. All rights reserved.

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