PUML1_DG-115 查看數據表（PDF） - NXP Semiconductors.
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PUML1_DG-115
NXP Semiconductors.
PUML1_DG-115 Datasheet PDF : 12 Pages
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NXP Semiconductors
PUML1/DG
50 V, 200 mA NPN general-purpose transistor/100 mA NPN RET
Table 5. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Ptot
total power dissipation
TR2 (resistor-equipped transistor)
Tamb ≤ 25 °C
[1] -
VCBO
collector-base voltage
open emitter
-
VCEO
collector-emitter voltage
open base
-
VEBO
emitter-base voltage
open collector
-
VI
input voltage
positive
-
negative
-
IO
output current
ICM
peak collector current
Ptot
total power dissipation
Per device
-
single pulse;
-
tp ≤ 1 ms
Tamb ≤ 25 °C
[1] -
Ptot
Tj
Tamb
Tstg
total power dissipation
junction temperature
ambient temperature
storage temperature
Tamb ≤ 25 °C
[1] -
-
−55
−65
Max Unit
200
mW
50
V
50
V
10
V
+40
V
−10
V
100
mA
100
mA
200
mW
300
mW
150
°C
+150 °C
+150 °C
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
300
Ptot
(mW)
200
006aab254
100
0
−75
−25
25
75
FR4 PCB, standard footprint
Fig 1. Per transistor: Power derating curve
125
175
Tamb (°C)
PUML1_DG_1
Product data sheet
Rev. 01 — 14 July 2008
© NXP B.V. 2008. All rights reserved.
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