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P87LPC767BD 查看數據表(PDF) - Philips Electronics

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P87LPC767BD Datasheet PDF : 60 Pages
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Philips Semiconductors
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
Product data
87LPC767
P2.0–P2.1
VSS
VDD
6, 7
I/O Port 2: Port 2 is a 2-bit I/O port with a user-configurable output type. Port 2 latches are configured in the
quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined by
the PRHI bit in the UCFG1 configuration byte. The operation of port 2 pins as inputs and outputs
depends upon the port configuration selected. Each port pin is configured independently. Refer to the
section on I/O port configuration and the DC Electrical Characteristics for details.
Port 2 also provides various special functions as described below.
7
O
P2.0 X2
Output from the oscillator amplifier (when a crystal oscillator option is
selected via the EPROM configuration).
CLKOUT CPU clock divided by 6 clock output when enabled via SFR bit and in
conjunction with internal RC oscillator or external clock input.
6
I
P2.1 X1
Input to the oscillator circuit and internal clock generator circuits (when
selected via the EPROM configuration).
5
I Ground: 0 V reference.
15
I Power Supply: This is the power supply voltage for normal operation as well as Idle and
Power Down modes.
SPECIAL FUNCTION REGISTERS
Name
Description
SFR
Address MSB
E7
E6
ACC*
Accumulator
E0h
C7
C6
ADCON#* A/D Control
C0h ENADC
AUXR1# Auxiliary Function Register A2h
KBF BOD
F7
F6
B*
B register
F0h
CMP1#
Comparator 1 control
register
ACh
CMP2#
Comparator 2 control
register
ADh
DAC0# A/D Result
C5h
DIVM#
CPU clock divide-by-M
control
95h
DPTR: Data pointer (2 bytes)
DPH
Data pointer high byte
83h
DPL
Data pointer low byte
82h
I2CFG#* I2C configuration register
CF
CE
C8h/RD SLAVEN MASTRQ
C8h/WR SLAVEN MASTRQ
I2CON#* I2C control register
DF
DE
D8h/RD RDAT ATN
I2DAT# I2C data register
D8h/WR CXA
D9h/RD RDAT
IDLE
0
D9h/WR XDAT
x
AF
AE
IEN0*
Interrupt enable 0
A8h
EA
EWD
EF
EE
IEN1#* Interrupt enable 1
E8h
ETI
BF
BE
IP0*
Interrupt priority 0
B8h
PWD
IP0H#
Interrupt priority 0 high byte B7h
PWDH
Bit Functions and Addresses
E5
E4
E3
E2
C5
C4
C3
C2
ADCI ADCS RCCLK
BOI LPEP SRST
0
F5
F4
F3
F2
E1
C1
AADR1
F1
LSB
E0
C0
AADR0
DPS
F0
Reset
Value
00h
00h
02h1
00h
CE1
CP1
CN1
OE1
CO1 CMF1 00h1
CE2
CP2
CN2
OE2
CO2 CMF2 00h1
00h
00h
CD
0
CLRTI
DD
DRDY
CDR
0
x
AD
EBO
ED
EC1
BD
PBO
PBOH
CC
TIRUN
TIRUN
DC
ARL
CARL
0
x
AC
ES
EC
EAD
BC
PS
PSH
CB
DB
STR
CSTR
0
x
AB
ET1
EB
BB
PT1
PT1H
CA
DA
STP
CSTP
0
x
AA
EX1
EA
EC2
BA
PX1
PX1H
C9
CT1
CT1
D9
MASTER
XSTR
0
x
A9
ET0
E9
EKB
B9
PT0
PT0H
C8
CT0
CT0
D8
XSTP
0
x
A8
EX0
E8
EI2
B8
PX0
PX0H
00h
00h
00h1
80h1
80h
00h
00h1
00h1
00h1
2001 Aug 07
6

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