V360EPC-33 查看數據表（PDF） - Unspecified
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V360EPC-33 Datasheet PDF : 18 Pages
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V360EPC
Table 14: Local Bus Timing Parameters for Vcc = 5 Volts +/- 5%
33MHz
50MHz
# Symbol
Description
Notes Min Max Min Max Units
1 TC LCLK/MEMCLK period
2 TCH LCLK/MEMCLK high time
3 TCL LCLK/MEMCLK low time
4 TSU Synchronous input setup
4a
TSU
Synchronous input setup
(BLAST,BTERM)/(BURST, ERR)
30
20
ns
1
12
9
ns
1
12
9
ns
2
7
6
ns
8
7
ns
4b TSU Synchronous input setup (ADS/LREQ)
4c
TSU
Synchronous input setup (address, data,
byte enables)
6
5
ns
8
6
ns
4d
TSU
Synchronous input setup for read data
when in local bus master mode
5
5
ns
4e
TSU
Synchronous input setup for (READY, W/
R, HOLDA)/(RDY, R/W, LBGRT)
5
4
5 TH Synchronous input hold
6 TCOV LCLK/MEMCLK to output valid delay
6a
TCOV
LCLK/MEMCLK to output valid delay
(address, data, byte enable, parity)
2
2 ns
3
3 14 3 10 ns
3 15 3 12 ns
7 TCZO LCLK to output driving delay
8 TCOZ LCLK/MEMCLK to high impedance delay
9 TRST Reset period when LRST used as input
3 15 3 12 ns
4
3 15 3 12 ns
16·TC
16·TC
ns
1. Measured at 1.5V.
2. All local bus signals except those in 4a, 4b, 4c, 4d and 4e.
3. All local bus signals except those in 6a.
4. READY, BLAST, ADS are driven to high impedance at the falling edge of LCLK.
Copyright © 1998, V3 Semiconductor Corp.
V360EPC Data Sheet Rev 1.2
15
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