
MT8843
DATA
DCLK
tDCD
tCDD
tR
tF
tCL
tCH
tR
tF
Figure 11 - DATA and DCLK Mode 0 Output Timing
VHM
VCT
VLM
VHM
VCT
VLM
tRF
tRR
VHM
DR
VCT
VLM
tRL
Figure 12 - DR Output Timing
TIP/RING
(A/B)
WIRES
DATA
DCLK
DR
start
stop
start
stop
start
stop
b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2
tIDD
start
start
start
b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2
stop
stop
stop
1/fDCLK0
tRL
tCRD
Figure 13 - Serial Data Interface Timing (MODE 0)
5-46