
Clock relationships (DivMode = 2:1)
Cycle
1
2
SysClock
(input)
PClock
(internal)
Note (output)
tDM
Data
tDO
Data
µPD30550
3
4
Data
Data
Note (input)
Data
tDS
tDH
Data
Note SysAD(63:0), SysADC(7:0), SysCmd(8:0), SysID(2:0)
Power-on sequence
VDD
50%
tDF
tDF
Data
Data
VDDIO
50%
Data Sheet U15700EJ1V0DS
21