SCC68681E1N40 查看數據表（PDF） - NXP Semiconductors.

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SCC68681E1N40

Dual asynchronous receiver/transmitter (DUART)

NXP Semiconductors. 

Philips Semiconductors

Dual asynchronous receiver/transmitter (DUART)

Product data

SCC68681

RESETN

tRES

SD00109

Figure 3. Reset Timing

X1/CLK

A1–A4

RWN

CSN

D0–D7

DTACKN

tCSC

tAS

tRWS

tAH

tRWH

tCSW

tDD

tDF

tDAL

tCSD

tDCR

tDAH

tDAT

SD00110

Figure 4. Bus Timing (Read Cycle)

X1/CLK

A1–A4

RWN

CSN

tCSC

tAS

tRWS

tAH

tRWH

tCSW

D0–D7

DTACKN

tDS

tDH

tCSD

NOTE:

DACKN requires two rising edges of X1 clock after CEN is low.

tDCW

tDAH

tDAT

Figure 5. Bus Timing (Write Cycle)

SD00111

2004 Apr 06

22

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