SCC68681E1N40 查看數據表（PDF） - NXP Semiconductors.
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SCC68681E1N40 Datasheet PDF : 29 Pages
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Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product data
SCC68681
AC CHARACTERISTICS 1, 2, 3, 4
Tamb = –40 °C to +85 °C; VCC = 5.0 V ± 10%
SYMBOL
PARAMETER
LIMITS
Min
Typ3
Max
UNIT
Reset Timing (See Figure 3)
tRES
RESETN pulse width
Bus Timing (See Figures 4, 5, 6)
200
ns
tAS
tAH
tRWS
tRWH
tCSW
tCSD5
tDD
tDF
tDS
tDH
tDAL
tDCR
tDCW
tDAH
tDAT
tCSC6
A1–A4 setup time to CSN LOW
A1–A4 hold time from CSN LOW
RWN setup time to CSN HIGH
RWN hold time to CSN HIGH
CSN HIGH pulse width
CSN or IACKN HIGH from DTACKN LOW
Data valid from CSN or IACKN LOW
Data bus floating from CSN or IACKN HIGH7
Data setup time to CLK HIGH
Data hold time from CSN HIGH
DTACKN LOW from read data valid
DTACKN LOW (read cycle) from CLK HIGH
DTACKN LOW (write cycle) from CLK HIGH
DTACKN HIGH from CSN or IACKN HIGH
DTACKN HIGH impedance from CSN or IACKN HIGH
CSN or IACKN setup time to clock HIGH
Port Timing (See Figure 7)
10
–
–
ns
100
–
–
ns
0
–
–
ns
0
–
–
ns
90
–
–
ns
20
–
–
ns
–
–
175
ns
–
–
100
ns
100
–
–
ns
20
–
–
ns
0
–
–
ns
–
–
125
ns
–
–
125
ns
–
–
100
ns
–
–
125
ns
90
–
–
ns
tPS
Port input setup time to CSN LOW
tPH
Port input hold time from CSN HIGH
tPD
Port output valid from CSN HIGH
Interrupt Reset Timing (See Figure 9)
0
–
–
ns
0
–
–
ns
–
–
400
ns
INTRN or OP3–OP7 when used as interrupts negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
tIR
Reset command (delta break interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
–
–
300
ns
–
–
300
ns
–
–
300
ns
–
–
300
ns
–
–
300
ns
–
–
300
ns
Clock Timing (See Figure 8)
tCLK
fCLK8
tCTC
fCTC
tRX
fRX
tTX
fTX
X1/CLK HIGH or LOW time
X1/CLK frequency
CTCLK HIGH or LOW time
CTCLK frequency
RxC HIGH or LOW time
RxC frequency
(16×)
(1×)
TxC HIGH or LOW time
TxC frequency
(16×)
(1×)
100
–
–
0
3.6864 4.0
100
–
–
0
–
4.0
220
–
–
0
–
2.0
0
–
1.0
220
–
–
0
–
2.0
0
–
1.0
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
Transmitter Timing (See Figure 10)
tTXD
TxD output delay from TxC external clock input on IP pin
tTCS
Output delay from TxC LOW at OP pin to TxD data output
Receiver Timing (See Figure 11)
–
–
350
ns
–
–
150
ns
tRXS
tRXH
RxD data setup time before RxC HIGH at external clock input on IP pin
RxD data hold time after RxC HIGH at external clock input on IP pin
240
–
–
ns
200
–
–
ns
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature and VCC supply
range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with
a transition time of 20 ns maximum. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input
voltages of 0.8 V and 2.0 V as appropriate.
3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150 pF, except interrupt outputs. Test condition for interrupt outputs: CL = 50 pF, RL = 2.7 kΩ to VCC.
5. This specification will impose maximum 68000 CPU CLK to 6MHz. Higher CPU CLK can be used if repeating bus reads are not performed.
Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
6. This specification imposes a lower bound on CSN and IACKN LOW, guaranteeing that it will be LOW for at least 1 CLK period. This
requirement is made on CSN only to insure assertion of DTACKN and not to guarantee operation of the part.
7. This spec is made only to insure that DTACKN is asserted with respect to the rising edge of the X1/CLK pin as shown in the timing diagram,
not to guarantee operation of the part. If setup time is violated, DTACKN may be asserted as shown, or may be asserted 1 clock cycle later.
8. Operation to 0 MHz is assured by design. Minimum test frequency is 2.0 MHz.
2004 Apr 06
21
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