NCV7518MWTXG 查看數據表（PDF） - ON Semiconductor
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NCV7518MWTXG Datasheet PDF : 37 Pages
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NCV7518, NCV7518A
ELECTRICAL CHARACTERISTICS (continued)
(4.75 V ≤ VCCX ≤ 5.25 V, VDD = VCCX, 4.5 V ≤ VLOAD ≤ 18 V, RSTB = VCCX, ENB = 0, −40°C ≤ TJ ≤ 150°C, unless otherwise specified.)
(Note 7)
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
GATE DRIVER OUTPUTS
GATX Output Resistance
GATX High Output Current
GATX Low Output Current
Turn-On Propagation Delay
Turn-Off Propagation Delay
Output Rise Time
RGATX
Output High or Low
200
350
500
W
IGSRC
VGATX = 0 V
−26.25
−
−9.5
mA
IGSNK
VGATX = VCC2
9.5
−
26.25 mA
tP(ON)
INX to GATx (Figure 4)
CSB to GATX (Figure 5)
−
−
1.0
ms
tP(OFF)
INX to GATX (Figure 4)
CSB to GATX (Figure 5)
−
−
1.0
ms
tR
20% to 80% of VCC2, CLOAD = 400 pF (Figure 4,
−
Note 8)
−
277
ns
Output Fall Time
tF
80% to 20% of VCC2, CLOAD = 400 pF (Figure 4,
−
Note 8)
−
277
ns
SERIAL PERIPHERAL INTERFACE (Figure 9) VCCX = 5.0 V, VDD = 3.3 V, FSCLK = 4.0 MHz, CLOAD = 200 pF
SO Supply Voltage
VDD
3.3 V Interface
5 V Interface
3.0
3.3
3.6
V
4.5
5.0
5.5
V
SCLK Clock Period
tSCLK
−
250
−
ns
Maximum Input Capacitance
CINX
Sl, SCLK (Note 8)
−
−
12
pF
SCLK High Time
tCLKH
SCLK = 2.0 V to 2.0 V
125
−
−
ns
SCLK Low Time
tCLKL
SCLK = 0.8 V to 0.8 V
125
−
−
ns
Sl Setup Time
tSISU
Sl = 0.8 V/2.0 V to SCLK = 2.0 V (Note 8)
25
−
−
ns
Sl Hold Time
tSIHD
SCLK = 2.0 V to Sl = 0.8 V/2.0 V (Note 8)
25
−
−
ns
SO Rise Time
tSOR
(20% VSO to 80% VDD) CLOAD = 200 pF (Note 8)
−
25
50
ns
SO Fall Time
tSOF
(80% VSO to 20% VDD) CLOAD = 200 pF (Note 8)
−
−
50
ns
CSB Setup Time
tCSBSU
CSB = 0.8 V to SCLK = 2.0 V (Note 8)
60
−
−
ns
CSB Hold Time
tCSBHD
SCLK = 0.8 V to CSB = 2.0 V (Note 8)
75
−
−
ns
CSB to SO Time
tCS−SO
CSB = 0.8 V to SO Data Valid (Note 8)
−
65
125
ns
SO Delay Time
SODLY
SCLK = 0.8 V to SO Data Valid (Note 8)
−
65
125
ns
Transfer Delay Time
CSDLY CSB Rising Edge to Next Falling Edge (Note 8) 1.6
−
−
ms
7. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise. Min/Max values are guaranteed by test,
design or statistical correlation.
8. Guaranteed by design.
INX
GAT X
50%
tP(OFF)
50%
tR
tF
80%
20%
tP(ON)
Figure 4. Gate Driver Timing Diagram − Parallel Input
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