NCV7518
PACKAGE PIN DESCRIPTION 32 PIN QFN EXPOSED PAD PACKAGE
Label
Description
FLTREF
Analog Fault Detect Threshold: 5 V Compliant
DRN0 − DRN5 Analog Drain Feedback
GAT0 − GAT5
Analog Gate Drive: 5 V Compliant
RSTB
Digital Master Reset Input: 3.3 V/5 V (TTL) Compatible
ENB
Digital Master Enable Input: 3.3 V/5 V (TTL) Compatible
IN0 − IN5
Digital Parallel Input: 3.3 V/5 V (TTL) Compatible
CSB
Digital Chip Select Input: 3.3 V/5 V (TTL) Compatible
SCLK
Digital Shift Clock Input: 3.3 V/5 V (TTL) Compatible
SI
Digital Serial Data Input: 3.3 V/5 V (TTL) Compatible
SO
Digital Serial Data Output: 3.3 V/5 V Compliant
FLTB
Digital Open-Drain Output: 3.3 V/5 V Compliant
VLOAD
Power Supply − Diagnostic References and Currents
VCC1
Power Supply − Low Power Path
GND
Power Return − Low Power Path − Device Substrate
VCC2
Power Supply − Gate Drivers
VDD
Power Supply − Serial Output Driver
VSS
Power Return − VLOAD, VCC2, VDD
EP
Exposed Pad − Connected to GND − Device Substrate
NCV7518
Figure 3. 32 Pin QFN Exposed Pad Pinout (Top View)
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