74LV595D(2016) 查看數據表（PDF） - NXP Semiconductors.

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74LV595D
(Rev.:2016)

8-bit serial-in/serial-out or parallel-out shift register; 3-state

NXP Semiconductors. 

Nexperia

74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

9,

05LQSXW



*1'

9,

6+&3LQSXW



*1'

92+

4 6RXWSXW

92/

90

W:

W UHF

90

W 3+/

90

PQD

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and

the master reset to shift clock (SHCP) recovery time

2(LQSXW

9,

*1'

9&&

RXWSXW

/2:WR2))

2))WR/2:

92/

92+

RXWSXW

+,*+WR2))

2))WR+,*+

*1'

90

W3/=

W3=/

W3+=

9;

9<

RXWSXWV

HQDEOHG

90

W3=+

RXWSXWV

GLVDEOHG

90

RXWSXWV

HQDEOHG

DDH

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig 12. Enable and disable times

Table 8. Measurement points

Supply voltage

Input

VCC

VCC < 2.7 V

VCC  2.7 V

VM

0.5VCC

1.5 V

Output

VM

0.5VCC

1.5 V

VX

VOL  0.1VCC

VOL  0.3 V

VY

VOH  0.1VCC

VOH  0.3 V

74LV595

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 18 March 2016

© Nexperia B.V. 2017. All rights reserved

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