CY7C1381D-100BZXI(2011) 查看數據表（PDF） - Cypress Semiconductor
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CY7C1381D-100BZXI Datasheet PDF : 34 Pages
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied .......................................... –55 °C to +125 °C
Supply Voltage on VDD Relative to GND ......–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND ..... –0.3 V to +VDD
DC Voltage Applied to Outputs
in Tri-State .........................................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................. –0.5 V to VDD + 0.5 V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0 °C to +70 °C
–40 °C to +85 °C
VDD
VDDQ
3.3 V–5%/+10% 2.5 V – 5%
to VDD
Neutron Soft Error Immunity
Parameter
LSBU
LMBU
SEL
Description
Logical Single-Bit Upsets
Logical Multi-Bit Upsets
Single Event Latch Up
Test Conditions
25 °C
25 °C
85 °C
Electrical Characteristics
Over the Operating Range [21, 22]
Parameter
Description
VDD
VDDQ
Power Supply Voltage
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage [21]
VIL
Input LOW Voltage [21]
IX
Input Leakage Current
except ZZ and MODE
Input Current of MODE
Input Current of ZZ
IOZ
Output Leakage Current
IDD
VDD Operating Supply
Current
Test Conditions
for 3.3 V I/O
for 2.5 V I/O
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
for 2.5 V I/O
for 3.3 V I/O
for 2.5 V I/O
GND VI VDDQ
Input = VSS
Input = VDD
Input = VSS
Input = VDD
GND VI VDD, Output Disabled
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5 ns cycle, 133 MHz
10 ns cycle, 100 MHz
Typ Max[20] Unit
361
394 FIT/Mb
0
0.01 FIT/Mb
0
0.1 FIT/Dev
Min
3.135
3.135
2.375
2.4
2.0
–
–
2.0
1.7
–0.3
–0.3
–5
Max Unit
3.6
V
VDD
V
2.625
V
–
V
–
V
0.4
V
0.4
V
VDD + 0.3V V
VDD + 0.3V V
0.8
V
0.7
V
5
A
–30
–
A
–
5
A
–5
–
A
–
30
A
–5
5
A
–
210
mA
–
175
mA
Notes
20. No LMBU or SEL events occurred during testing; this column represents a statistical c2, 95% confidence limit calculation. For more details refer to Application Note
AN54908, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates.
21. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
22. Tpower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05544 Rev. *I
Page 21 of 34
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