CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
TAP Timing
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
1
2
3
4
5
6
Test Clock
(TCK)
Test Mode Select
(TMS)
t TH
tTL
tTMSS tTMSH
t CYC
tTDIS tTDIH
Test Data-In
(TDI)
t TDOV
Test Data-Out
(TDO)
t TDOX
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range [13, 14]
Parameter
Description
Min
Clock
tTCYC
TCK Clock Cycle Time
50
tTF
TCK Clock Frequency
–
tTH
TCK Clock HIGH Time
20
tTL
TCK Clock LOW Time
20
Output Times
tTDOV
TCK Clock LOW to TDO Valid
–
tTDOX
TCK Clock LOW to TDO Invalid
0
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
5
tTDIS
TDI Setup to TCK Clock Rise
5
tCS
Capture Setup to TCK Rise
5
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
5
tTDIH
TDI Hold after Clock Rise
5
tCH
Capture Hold after Clock Rise
5
Notes
13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Max
–
20
–
–
10
–
–
–
–
–
–
–
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document Number: 38-05544 Rev. *I
Page 16 of 34
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