74HC160 查看數據表（PDF） - NXP Semiconductors.

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74HC160

Presettable synchronous BCD decade counter; asynchronous reset

NXP Semiconductors. 

Nexperia

74HC160

Presettable synchronous BCD decade counter; asynchronous reset

6. Functional description

Table 3. Function table[1]

Operating mode

Reset (clear)

Parallel load

Count

Hold (do nothing)

Inputs

Outputs

MR

CP

CEP CET PE

Dn

Qn

TC

L

X

X

X

X

X

L

L

H



X

X

I

I

L

L

H



X

X

I

h

H

[2]

H



h

h

h

X

count [2]

H

X

I

X

h

X

qn

[2]

H

X

X

I

h

X

qn

L

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;

L = LOW voltage level;

I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;

qn = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition;

X = don’t care;

 = LOW-to-HIGH clock transition.

[2] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH);

Fig 7. State diagram

































DDD

74HC160

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 27 September 2016

© Nexperia B.V. 2017. All rights reserved

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