MX97103FC 查看數據表（PDF） - Macronix International
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MX97103FC Datasheet PDF : 13 Pages
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PCI SHARED SIGNALS A.C. TIMING WAVEFORM
CLK
t1
OUTPUT
INPUT
1.5V
1.5V Valid
t3
Valid
t5
t2
t4
t6
MX97103
PARAMETER
CLK signal valid delay
CLK to signal invalid delay
Hi-Z to active delay from CLK
Active to Hi-Z delay from CLK
Input signal valid setup time before CLK
Input signal hold time from CLK
SYMBOL
t1
t2
t3
t4
t5
t6
MIN.
2ns
2ns
7ns
0ns
MAX.
11ns
NOTES
CL=50pF
28ns
PCI SIDEBAND SIGNALS A.C. TIMING WAVEFORM
CLK
t1
OUTPUT
INPUT
1.5V
1.5V Valid
t3
Valid
t5
t2
t4
t6
PARAMETER
CLK to sideband signal valid delay
CLK to signal invalid delay
Hi-Z to active delay from CLK
Active to Hi-Z delay from CLK
Sideband signal valid setup time before CLK
Input signal hold time from CLK
SYMBOL
t1
t2
t3
t4
t5
t6
MIN.
2ns
2ns
12ns
0ns
MAX.
12ns
NOTES
CL=50pF
28ns
P/N:PM0564
REV. 1.0, FEB. 23, 1999
8
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