MB90091A 查看數據表（PDF） - Fujitsu
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MB90091A Datasheet PDF : 46 Pages
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(4) Address data hold timing
Parameter
ROM read cycle
Address valid delay
Address invalid delay
Read data setup
Read data hold
TCS, FCS active delay
TCS, FCS inactive delay
* : Dot clock = 84 to 42 MHz
MB90091A
(VCC = AVCC = 5.0 V ± 5%, VSS = AVSS = 0 V, Ta = 0°C to +70°C)
Symbol
Pin
Values
Unit
Min.
Max.
trcyc
—
Dot clock* x 8
—
tav
RA0 to
—
tai
RA15
0
30
ns
—
ns
tds
30
RD0 to RD7
tdh
0
—
ns
—
ns
tca
—
TCS, FCS
tci
0
22
ns
—
ns
8
1
2
DOCK
t rcyc
3
4
5
6
7
8
1
0.2 V CC
RA0 to 15
t av
TCS, FCS
t ci
t ca
RD0 to 7
0.8 V CC
0.2 V CC
t ai
0.8 V CC
0.2 V CC
t ds
t dh
0.8 V CC
0.2 V CC
15
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