LF48410 查看數據表（PDF） - LOGIC Devices

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LF48410

1024 x 24-bit Video Histogrammer

LOGIC Devices 

DEVICES INCORPORATED

LF48410

1024 x 24-bit Video Histogrammer

HISTOGRAM MODE

When the LF48410 is in this mode, the

chip is configured as shown in Figure

1. The memory array keeps track of

how many times a particular pixel

value is used in a video image. The

pixel value is input on PIN9-0 and is

latched on the rising edge of CLK.

Data at the address defined by PIN9-0

is read out of the memory array and

incremented by one. The data is then

written back to the memory array, in

the same location it was read from,

and is also output on DIO23-0 (if RD is

LOW). As long as START is LOW,

the device will be enabled for Histo-

gram Mode. When START is HIGH,

the device will still read pixel values,

but the addres-sed data will not be

incremented. The unchanged data is

output on DIO23-0 and is not written

back to the memory array (writing is

disabled). START is delayed inter-

nally three clock cycles to match the

latency of the address generator.

HISTOGRAM ACCUMULATE

MODE

When the LF48410 is in this mode, the

chip is configured as shown in Figure

2. This mode is used to calculate the

Cumulative Distribution Function of

a video image. Before this can be

done, the histogram of the image

must already be in the memory array.

The internal counter is used to

generate address data for the memory

array. Data at the address defined by

the counter is read out of the memory

array and added to the sum of the

data from all previous address

locations. This new value is written

back to the memory array, in the

same location where the last read

occurred, and is also output on

DIO23-0 (if RD is LOW). After all

memory locations with histogram

data are accumulated, the memory

array will contain the Cumulative

Distribution Function.

After this mode is selected, the

internal counter and all data path

registers are reset to zero when

FIGURE 1. HISTOGRAM MODE

RAM ARRAY

DATA IN

DATA OUT

ADDRESS WR

10

PIN9-0

ADDRESS

"0"

GENERATOR

"1"

START

CONTROL

CLK

TO ALL REGISTERS

FIGURE 2. HISTOGRAM ACCUMULATE MODE

24

DIO

I/F

DIO23-0

RD

CLK

(TO ALL REGISTERS)

START

RAM ARRAY

DATA IN

DATA OUT

ADDRESS WR

ADDRESS

GENERATOR

"0"

COUNTER

CONTROL

24

DIO

I/F

DIO23-0

RD

START is set LOW. Every rising edge

of CLK causes the counter to incre-

ment its output by one until the

counter reaches a value of 1023. At

this point, the counter will hold the

value of 1023 and writing to the

memory array will be disabled. As

long as START is LOW, the device

will be enabled for Histogram Accu-

mulate Mode. When START is HIGH,

the counter will still increment its

address values, but the addressed

data will not be added to anything.

The unchanged data is output on

DIO23-0 and is not written back to the

memory array (writing is disabled).

START is delayed internally three

clock cycles to match the latency of

the address generator.

LOOK UP TABLE MODE

When the LF48410 is in this mode, the

chip is configured as shown in Figure

3. This mode is used to perform fixed

transformation functions on pixel

values. The transformation function

can be loaded into the memory array

in Look Up Table Write Mode,

Asynchronous 16/24 Mode, or

Histogram Accumulate Mode. In

Look Up Table Write Mode, data is

loaded into the memory array using

DIN23-0, CLK, and START. The

internal counter is used to generate

address data for the memory array.

When START goes LOW, the counter

is reset to zero. As long as START is

LOW, data on DIN23-0 is latched on

the rising edge of CLK and loaded

Video Imaging Products

3

08/08/2000–LDS.48410-L

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