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WM8766 查看數據表(PDF) - Cirrus Logic

零件编号
产品描述 (功能)
生产厂家
WM8766
Cirrus-Logic
Cirrus Logic 
WM8766 Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Production Data
DIGITAL AUDIO INTERFACE – SLAVE MODE
WM8766
BCLK
WM8766
DAC
LRCLK
DIN1/2/3
3
DSP/
DECODER
Figure 4 Audio Interface – Slave Mode
BCLK
LRCLK
DIN1/2/3
tBCH
tBCL
tBCY
tDS
tLRH
tLRSU
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCLK cycle time
tBCY
BCLK pulse width high
tBCH
BCLK pulse width low
tBCL
LRCLK set-up time to BCLK
rising edge
tLRSU
LRCLK hold time from
tLRH
BCLK rising edge
DIN1/2/3 set-up time to
tDS
BCLK rising edge
DIN1/2/3 hold time from
tDH
BCLK rising edge
Table 3 Digital Audio Data Timing – Slave Mode
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
10
ns
10
ns
w
PD Rev 4.1 July 2005
9

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