WM8766 查看數據表（PDF） - Cirrus Logic
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WM8766 Datasheet PDF : 36 Pages
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WM8766
MPU INTERFACE TIMING
ML/I2S
MC/IWL
tSCY
tSCH
tSCL
Production Data
tCSL
tCSH
tCSS
tSCS
MD/DM
tDSU
tDHO
LSB
Figure 6 SPI Compatible Control Interface Input Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated
PARAMETER
SYMBOL
MIN
MC/IWL rising edge to ML/I2S rising edge
tSCS
60
MC/IWL pulse cycle time
tSCY
80
MC/IWL pulse width low
tSCL
30
MC/IWL pulse width high
tSCH
30
MD/DM to MC/IWL set-up time
tDSU
20
MC/IWL to MD/DM hold time
tDHO
20
ML/I2S pulse width low
ML/I2S pulse width high
tCSL
20
tCSH
20
ML/I2S rising to MC/IWL rising
tCSS
20
Table 4 3-wire SPI Compatible Control Interface Input Timing Information
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
w
PD Rev 4.1 July 2005
10
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