MSC8126TMP6400(2007) 查看數據表（PDF） - Freescale Semiconductor

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MSC8126TMP6400
(Rev.:2007)

Quad Digital Signal Processor

Freescale Semiconductor 

Figure 14 shows DSI asynchronous read signals timing.

HCS

HA[11–29]

HCID[0–4]

HDST

HRW1

HWBSn2

100

Electrical Characteristics

101

HDBSn1

HRDS2

HD[0–63]

112

103

107

104

106

102

105

109

HTA3

108

110

HTA4

111

Notes: 1. Used for single-strobe mode access.

2. Used for dual-strobe mode access.

3. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with

pull-down implementation.

4. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up

implementation.

Figure 14. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

Freescale Semiconductor

29

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