MSC8122TVT4800V(2006) 查看數據表（PDF） - Freescale Semiconductor

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MSC8122TVT4800V
(Rev.:2006)

Quad Core 16-Bit Digital Signal Processor

Freescale Semiconductor 

Design Considerations

• In CLKOUT synchronization mode (for 1.2 V devices), CLKOUT is the main clock to SDRAM. Use the

following connections:

— Connect the oscillator output through a buffer to CLKIN.

— Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using the

following guidelines:

• The maximum delay between the slave and CLKOUT must not exceed 0.7 ns.

• The maximum load on CLKOUT must not exceed 10 pF.

• Use a zero-delay buffer with a jitter less than 0.3 ns.

— All clock modes are valid in this clock scheme.

Note: See the Clock chapter in the MSC8122 Reference Manual for details.

• If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, PPBS can be disconnected.

Otherwise, it should be pulled up.

• The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are

used to configure the MSC8122 and are sampled on the deassertion of the PORESET signal. Therefore, they

should be tied to GND or VDDH or through a pull-down or a pull-up resistor until the deassertion of the PORESET

signal.

• When they are used, INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive)

signals must be pulled up.

• When the Ethernet controller is enabled and the SMII mode is selected, GPIO10 and GPIO14 must not be

connected externally to any signal line.

Note: For details on configuration, see the MSC8122 User’s Guide and MSC8122 Reference Manual. For

additional information, refer to the MSC8122 Design Checklist (AN2787).

4.4 External SDRAM Selection

The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However,

because of differences in timing characteristics among various SDRAM manufacturers, you may have use a faster

speed rated SDRAM to assure efficient data transfer across the bus. For example, for 166 MHz operation, you may

have to use 183 or 200 MHz SDRAM. Always perform a detailed timing analysis using the MSC8122 bus timing

values and the manufacturer specifications for the SDRAM to ensure correct operation within your system design.

The output delay listed in SDRAM specifications is usually given for a load of 30 pF. Scale the number to your

specific board load using the typical scaling number provided by the SDRAM manufacturer.

MSC8122 Technical Data, Rev. 13

4-4

Freescale Semiconductor

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