DLO31F-8A2 查看數據表（PDF） - Data Delay Devices

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DLO31F-8A2

TTL-INTERFACED, GATED DELAY LINE OSCILLATOR

Data Delay Devices 

DLO31F

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

Ambient Temperature: 25oC ± 3oC

Supply Voltage (Vcc): 5.0V ± 0.1V

Input Pulse:

High = 3.0V ± 0.1V

Low = 0.0V ± 0.1V

Source Impedance: 50Ω Max.

Rise/Fall Time:

3.0 ns Max. (measured

between 0.6V and 2.4V )

Pulse Width Low:

PWIN = 10 x Clock Period

Period:

PERIN = 20 x Clock Period

OUTPUT:

Load:

Cload:

Threshold:

1 FAST-TTL Gate

5pf ± 10%

1.5V (Rising & Falling)

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

OUT

PULSE

GENERATOR TRIG

GB

C1

DEVICE UNDER

TEST (DUT)

C2

FREQUENCY

COUNTER

IN

TRIG

OSCILLOSCOPE

Test Setup

TFALL

PWIN

PERIN

TRISE

INPUT

SIGNAL

2.4V

1.5V

0.6V

VIL

2.4V

1.5V

0.6V

VIH

TEO

OUTPUT

SIGNAL

1.5V

VOH

1.5V

VOL

Timing Diagram For Testing

Doc #98001

DATA DELAY DEVICES, INC.

4

3/17/98

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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