HD74HC4538 查看數據表（PDF） - Renesas Electronics
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HD74HC4538 Datasheet PDF : 14 Pages
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HD74HC4538
Quiescent
State Trigger Cycle (A Input) Trigger Cycle (B Input)
Reset
Retrigger
7
Trigger Input A
(Pin 4 or 12)
Trigger Input B
(Pin 5 or 11)
8
Reset Input CD
(Pin 3 or 13)
trr
21
9
Trigger-Control
3
Circuit Output
4
T2 Input
12
(Pin 2 or 14)
14
11
15
Vref Lower 13
Upper Reference 5
Circuit Output
13
Lower Reference 6
16
Circuit Output
17
Vref Upper
Reset Latch
1
Output
10
Q Output
2
19
(Pin 6 or 10)
tWQ
tWQ
24
20 23
25
22
tWQ+trr
tW (H)
A
50%
B
tPLH
Q
Q
tWQ
50%
tPHL
50%
50%
tPLH
tW (L)
tPHL
A
trr
B
tf
CD
50%
tTLH
Q
90%
10%
tTHL
tPLH
Q
90%
10%
tr
tW (L)
90%
10%
tPHL
50%
50%
50%
50%
tWQ+trr
(Retriggered Pulse)
Figure 2. Timing Diagram
Rev.2.00 Mar 30, 2006 page 7 of 13
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