CS7410-CM 查看數據表（PDF） - Cirrus Logic
零件编号
产品描述 (功能)
生产厂家
CS7410-CM Datasheet PDF : 39 Pages
| |||
CS7410
Pin
Signal Name Type
Description
25, 26, 27, 28,
29, 30, 31, 32,
33, 34, 35, 36
DRAM
Address[11..0]
O Memory Address Bus.
37
DR_RAS_L
O Memory Row Address Strobe
39
DR_CAS_L
O Memory Column Address Strobe
41
M_WE_L
O Memory Write Enable
47
M_AP_OE
O Memory Output Enable
Table 11. EDO DRAM Interface (Continued)
4.5 ROM/NVRAM Interface
The ROM/NVRAM Interface pins are described in Table 12. This interface connects to the non-volatile
memory that contains the firmware. The memory could be ROM, NVRAM (FLASH), EEPROM, or any com-
bination of these memory types. This interface can also connect to SRAM that would emulate a ROM on a
development system. The bus width is always 8 bits. Most of these pins are shared with the DRAM interface,
which operates simultaneously with the ROM/NVRAM interface. A number of pins are defined to accept con-
figuration input at power-up (see Table 7), allowing different branches to be taken in the firmware. A config-
uration resistor is required on pin PCM_DO_0 to select whether the processor will boot from internal or
external ROM.
Pin
11, 13, 15, 20,
21, 22, 23, 24
25, 26, 27, 28,
29, 30, 31, 32,
33, 34, 35, 36
3, 4, 5, 6, 7, 8, 9,
10
46
41
47
48
Signal Name
NVMem Data[7..0]
NVM_Addr[11..0]
Type
Description
B Memory Data Bus (shared with bits [7:0] of DRAM data
bus).
O Memory Address Bus[11..0] (shared with DRAM address
bus)
NVM_Addr[19..12]
O Memory Address Bus[19..12] (shared with bits [15..8] of
DRAM data bus).
NVM_Addr[20]
O Memory Address Bus[20] (DRAM BS_L pin).
NVM_WE_L
O NVRAM Write Enable (shared with DRAM WE_L pin)
NVM_OE_L
O NVRAM Write Enable (shared with DRAM WE_L pin)
NVM_CE_L
O ROM/NVRAM Chip Enable.
Table 12. ROM/NVRAM Interface
32
DS553PP1
Share Link: 